Design Criteria for Low Distortion in Fedback OpAmp Circuits by B. hernes, T. Saether

By B. hernes, T. Saether

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Here, is the bias voltage, assumed constant, is the parasitic capacitance in the drain node and is the drain current. When designing for high bandwidth it is often more important to keep the parasitic capacitance low, than to obtain low output conductance. By using minimum gate length, and thus keep the gate width small, the parasitic capacitance on drain will be minimum, but at the cost of higher output conductance. When setting all voltages except in (3-1) to zero, equation (3-3) is obtained.

This is due TLFeBOOK 38 Design Criteria for Low Distortion in Feedback Opamp Circuits to a combination of velocity saturation and mobility degradation. Thus, and are both low compared to gm for in this region. On the other hand, high GS-voltage, and thus high GS-overdrive, will make the saturation voltage high and increase the nonlinear coefficients associated with the DSterminal. This is the same situation as for the current source described in the previous subsection. 8V to keep all nonlinear coefficients small and the total distortion from the transistor on a minimum.

TLFeBOOK Chapter 2 Specification and Analysis of Nonlinear Circuits 21 The phasor method, carried out on an analog circuit, can be explained by the following procedure: 1. Find the order response and all voltages/currents that control nonlinear coefficients in the circuit. These will be further used to find nonlinear responses of higher order. The circuit excitation is the input voltage to the circuit, which runs at one or more frequencies. 2. Find the desired order nonlinear response and all voltages/currents that control nonlinear coefficients in the circuit.

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